An Optimal Flip Flop Design for Vlsi Power Minimization
نویسنده
چکیده
The power consumption is critically important in modern VLSI circuits especially for low-power applications. Optimization of power at the logic level is one of the most important tasks to minimize the power. Among logic components, latches and flip-flops are critical to the performance of digital systems. It is important to reduce the power dissipation in both clock distribution networks (CDN) and flip-flops. This paper presents a comparison of existing flip-flop classes in terms of transistor count, parasitic values and power dissipation. The operation of each flip-flop is analyzed and it is simulated using Tanner EDA in 250nm technology at room temperature in schematic level. And it reveals that the proposed design features the best performance in four FF designs under comparison.
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